In this paper we propose a methodology for synthesis of asynchronous systems that requires just few hours of classroom teaching, being interesting to be incorporated in the subject of logic design. Unfortunately, the topic of synthesis of asynchronous digital systems has been ignored or presents only a few numbers of teaching classes in most courses in electrical engineering, due the difficulty of different styles of asynchronous design, what requires many hours of classroom teaching. Synchronous digital systems have been presenting serious problems of implementation in DSM (deep sub-micron) VLSI technology, for which the asynchronous paradigm has become an interesting alternative. The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous. Both circuits were designed and implemented in an FPGA Virtex 5. The parameters evaluated are power consumption, area, and speed. This work compares the asynchronous microprocessor with a synchronous version. The ST control is based on a micropipeline used as a centralized generator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This work describes the different blocks of the microprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of the asynchronous central unit, according to the developed occupations and speeds. It has support for floating point operations, such as addition, subtraction, and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. The materials presented in this paper have been used in a number of undergraduate and graduate courses and have been well received by the students. This approach ensures that students can easily relate asynchronous design and optimization techniques to the corresponding synchronous techniques. This paper introduces asynchronous logic design in the context of the familiar synchronous logic, then provides a description of course modules developed for NULL Convention Logic (NCL), an asynchronous logic paradigm that is very similar to the synchronous paradigm. To meet this growing industry need, computer engineering students should be introduced to asynchronous circuit design to make them more marketable and more prepared for the challenges faced by the digital design community for years to come. ITRS shows that asynchronous circuits accounted for 11% of chip area in 2008, compared to 7% in 2007, and estimates they will account for 23% of chip area by 2014 and 35% of chip area by 2019. As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used in the semiconductor industry, as evidenced by the International Technology Roadmap for Semiconductors' (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues.
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